View PEDL9352-01_227721.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

OKI Semiconductor ML9352
128-Channel Organic EL Driver with Built-in RAM
PEDL9352-01
Issue Date:Dec. 27, 2002
Preliminary
GENERAL DESCRIPTION
The ML9352 is an LSI for dot matrix graphic organic EL devices carrying out bit map display. This LSI can drive a dot matrix graphic organic EL display panel under the control of microcomputer. Since all the functions necessary for driving a bit map type organic EL device are incorporated in a single chip, using the ML9352 makes it possible to realize a bit map type dot matrix graphic organic EL display system with only a few chips. Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip, it is possible to construct a graphic display system with a maximum of 128 x 32 dots. Since the organic EL drive voltage of the ML9352 can range as high as 30 V, the ML9352 is suited to drive on-vehicle panels that require high luminance and panels used in audio equipment.
FEATURES
* Direct display of the RAM data using the bit map method Display RAM data "1" ... Dot is displayed Display RAM data "0" ... Dot is not displayed * Display RAM capacity ML9352: 32 x 128 = 4096 dots * Organic EL Drive circuits 33 cathode outputs, 128 anode outputs * Microcomputer interface: Can select an 8-bit parallel or serial interface * Built-in oscillator circuit (Internal oscillator circuit/external clock input selectable) * A variety of commands Read/write of display data, display ON/OFF, normal/reverse display, all dots ON, write address setting, scroll start line setting, fixed display line number setting, anode pulse width adjustment, etc. * Power supply voltage Logic power supply: VDDA = VDDL = 2.7 to 5.5 V Organic EL Drive voltage: VDISPS = 18 to 30 V, VDISPC = 18 to 30 V * Package: Bare chip
1/53
PEDL9352-01
OKI Semiconductor
ML9352
BLOCK DIAGRAM
SEG127 COMS1 COM31 COM0 SEG0 VDDA VDISPC VDISPS VEL ELSEL REL1 REL2 VDDL VSSA VSSS VSSC VSSL TEST0 TEST1 TEST2 TEST3 TEST4
Oscillator circuit Display data latch circuit
Voltage regulator
Anode drivers
Cathode drivers
COM output state selection circuit Display timing generator circuit
CCM CL
Write address circuit
Display data RAM 128 x 32
TEST5 TEST6
Column address circuit
Line address
I/O Buffer
CLS ROSC
Command decoder
Status
MPU Interface
WR (R/W)
D6 (SCL)
D7 (SI)
RD (E)
CS1
CS2
RES
C86
D5
D4
D3
D2
P/S
A0
D1
D0
2/53
PEDL9352-01
OKI Semiconductor
ML9352
PIN DESCRIPTION
Function Pin name Number of pins l/O Description This is an 8-bit bi-directional data bus that can be connected to an 8-bit or 16-bit standard MPU data bus. When a serial interface is selected (P/S = "H"): D0 to D7 8 l/O D7: Serial data input pin (SI) D6: Serial clock input pin (SCL) In this case, D0 to D5 will be in the Hi-Z state. D0 to D7 will all be in the Hi-Z state when the chip select is in the inactive state. Normally, the lowest bit of the MPU address bus is connected. A0 1 I Set this pin to "H" when writing or reading display data, and set to "L" when entering any other control command or writing any other control data. Initial setting is made by making RES = "L". The reset operation is made during the active level of the RES signal. These are the chip select signals. The Chip Select of the LSI becomes active when CS1 is "L" and also CS2 is "H" and allows the input/output of data or commands. The active level of this signal is "L" when connected to an 80-series MPU. RD (E) This terminal is connected to the RD signal of the 80-series MPU, and the data bus of the ML9352 goes into the output state when this signal is "L". The active level of this signal is "H" when connected to a 68-series MPU. This pin will be the Enable clock input pin when connected to a 68-series MPU. The active level of this signal is "L" when connected to an 80-series MPU. WR (R/W) This terminal is connected to the WR signal of the 80-series MPU. The data on the data bus is latched into the ML9352 at the rising edge of the WR signal. When connected to a 68-series MPU, this pin becomes the input pin for the Read/Write control signal. R/W = "H": Read, R/W = "L": Write This is the pin for selecting the MPU interface type. (This pin has a pull-down resistor.) C86 = "H": 68-Series MPU interface C86 = "L": 80-Series MPU interface
RES CS1 CS2
1
I
2
I
MPU Interface 1 I
1
I
C86
1
I
3/53
PEDL9352-01
OKI Semiconductor
ML9352
Function
Pin name
Number of pins
l/O
Description This is the pin for selecting parallel data input or serial data input. (This pin has a pull-down resistor.) P/S= "H": Serial data Input P/S= "L": Parallel data input The pins of the LSI have the following functions depending on the state of P/S input.
MPU Interface
P/S
1
I
P/S "H" "L"
Data/command A0 A0
Data SI (D7) D0 to D7
Read/Write Write only RD, WR
Serial clock SCL (D6)
CLS Oscillator circuit ROSC
1
I
When P/S is "H", D0 to D5 will go into the Hi-Z state. In this condition, the data on the lines D0 to D5 can be "H", "L" or open. The pins RD (E) and WR (R/W) should be tied to either the "H" level or the "L" level. During serial data input, it is not possible to read the display data in the RAM. This is the pin for selecting whether to enable or disable the internal oscillator circuit for the display clock. (This pin has a pull-down resistor.) CLS = "L": The internal oscillator circuit is enabled. CLS = "H": The internal oscillator circuit is disabled (External input). When CLS = "H", the display clock is input at the pin CL. This is the pin for adjusting the frequency of the internal oscillator circuit. Connecting the pin to VSSL allows the oscillation frequency to be lowered by 16%. Normally, leave this pin open. This is the display clock input/output pin. The function of this pin will be as follows depending on the state of and CLS signal.
1
I
Display timing generator circuit
CL
1
l/O
CLS "L" "H"
CL Output Input
Power supply circuit
CCM VDDA VSSA VDDL VSSL VDISPS VSSS VDISPC VSSC VEL
1 1 1 1 1 3 3 2 2 1
O -- -- -- -- -- -- -- -- I
ELSEL
1
I
REL1,2
2
I
Internal cathode timing output pin *1 Power supply pin for the analog circuit. *2 Ground pin for the analog circuit. *1 Power supply pin for the logic circuit. *2 Ground pin for the logic circuit. Power supply pin for the organic EL anode drive circuit. *2 Ground pin for the organic EL anode drive circuit. Power supply pin for the organic EL cathode drive circuit. *2 Ground pin for the organic EL cathode drive circuit. Input pin for the anode driver output current adjusting voltage. An input voltage is effective when ELSEL = "H". Pin that selects anode driver output current adjusting voltage. (This pin has a pull-down resistor.) When ELSEL = "L", the internally regulated voltage is selected; when ELSEL = "H", the VEL pin voltage is selected. Anode driver output current adjusting external resistor connection pins.
*1 *2
Make VDDA and VDDL have the same potential. Make VSSA, VSSL, VSSS, and VSSC have the same potential.
4/53
PEDL9352-01
OKI Semiconductor
ML9352
Function
Pin name SEG0 to SEG127 COM0 to COM31 COMS1 TEST0 TEST1 TEST2
Number of pins 128 32 1 1 1 1
l/O O O O I I I Anode driver output pins
Description
Organic EL drive output
Output pins for the cathode driver outputs for dot display Output pins for the cathode driver outputs for static display These pins are used to test the IC chip. Leave these pins open during normal operation. Input pin to control the TEST5 pin (internally regulated voltage monitor pin). TEST3 has a pull-down resistor. When TEST3 is "H", it outputs an internally regulated voltage (Vreg), and when "L" it will go into the Hi-Z state. This pin is used to test the IC chip. Leave this pin open during normal operation. Internally regulated voltage monitor pin This pin is used to test the IC chip. Leave this pin open during normal operation.
TEST3 Test pin TEST4 TEST5 TEST6
1
I
1 1 1
I O O
5/53
PEDL9352-01
OKI Semiconductor
ML9352
FUNCTIONAL DESCRIPTION
MPU Interface * Selection of interface type The ML9352 carries out data transfer using either the 8-bit bi-directional data bus (D7 to D0) or the serial data input line (SI). Either the 8-bit parallel data input or serial data input can be selected as shown in Table 1 by setting the P/S pin to the "H" or the "L" level. Table 1
P/S L: Parallel input H: Serial input CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD RD -- WR WR -- C86 C86 -- D7 D7 SI D6 D6 SCL D5 to D0 D5 to D0 (HZ)
A dash (--) indicates that the pin can be tied to the "H" or the "L" level. * Parallel interface When the parallel interface is selected, (P/S = "L"), it is possible to connect this LSI directly to the MPU bus of either an 80-series MPU or a 68-series MPU as shown in Table 2 depending on whether the pin C86 is set to "H" or "L". Table 2
C86 H L Type H: 68-Series MPU bus L: 80-Series MPU bus CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD E RD WR R/W WR D7 to D0 D7 to D0 D7 to D0
The data bus signals are identified as shown in Table 3 below depending on the combination of the signals A0, RD(E), and WR(R/W) of Table 2. Table 3
Common A0 Display data read Display data write Status read Control data write (command) 1 1 0 0 68-Series R/W 1 0 1 0 0 1 0 1 80-Series RD WR 1 0 1 0
6/53
PEDL9352-01
OKI Semiconductor
ML9352
Serial Interface When the serial interface is selected (P/S = "H"), the serial data input (SI) and the serial clock input (SCL) can be accepted if the chip is in the active state (CS1 = " L" and CS2 = "H"). The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data is read in from the serial data input pin in the sequence D7, D6, ... , D0 at the rising edge of the serial clock input, and is converted into the 8-bit paralled data at the rising edge of the 8th serial clock pulse and processed further. The identification of whether the serial data is display data or command is judged based on the A0 input, and the data is treated as display data when A0 is "H" and as command when A0 is "L". The A0 input is read in and identified at the rising edge of the (8 x n) th serial clock pulse after the chip has become active. Figure 1 shows the signal chart of the serial interface. (When the chip is not active, the shift register and the counter are reset to their initial states. No data read out is possible in the case of the serial interface. It is necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL signal. We recommend verification of operation in an actual unit.)
CS1 CS2 SI SCL A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 1 * Chip select The ML9352 has the two chip select pins CS1 and CS2, and the MPU interface or the serial interface is enabled only when CS1 = "L" and CS2 = "H". When the chip select signals are in the inactive state, the D0 to D7 lines will be in the high impedance state and the inputs A0, RD, and WR will not be effective. When the serial interface has been selected, the shift register and the counter are reset. * Accessing the display data RAM and the internal registers Accessing the ML9352 from the MPU side requires merely that the cycle time (tCYC) be satisfied, and high speed data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the ML9352 carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data bus. For example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus holder, and is then written into the display data RAM before the next data read cycle. When the MPU reads out data in the display data RAM, read data is held in the bus holder during the first data read cycle (dummy) and is read out on the system bus from the bus holder during the next data read cycle. There is a restriction on the read sequence of the display data RAM, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading. Therefore, always one dummy read is necessary immediately after setting the address or after a write cycle. This relationship is shown in Figures 2(a) and 2(b).
7/53
PEDL9352-01
OKI Semiconductor
ML9352
* Data write
MPU WR DATA Internal timing BUS Holder Write Signal N Latch N N+1 N+2 N+3 N+1 N+2 N+3
Figure 2(a) * Data read
WR MPU RD DATA Address Preset Internal timing Read Signal Column Address BUS Holder Preset N N Increment N+1 n n+1 N+2 n+2 N N n n+1
Address Set #n
Dummy Read
Data Read #n
Data Read #n+1
Figure 2(b) * Busy flag The busy flag being "1" indicates that the ML9352 is carrying out internal operations, and hence no instruction other than a status read instruction is accepted during this period. The busy flag is output at pin D7 when a status read instruction is executed. If the cycle time (tCYC) is established, there is no need to check this flag before issuing every command and hence the processing performance of the MPU can be increased greatly.
8/53
PEDL9352-01
OKI Semiconductor
ML9352
Display data RAM * Display data RAM This is the RAM storing the dot data for display and has an organization of 32 x 128 bits. It is possible to access any required bit by specifying the write address and the column address. Since the display data D7 to D0 from the MPU corresponds to the organic EL display in the direction of the common lines as shown in Figure 3. Also, since the display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the signal read operation for the organic EL drive. Consequently, the display is not affected by flickering, etc., even when the display data RAM is accessed asynchronously during the organic EL display operation.
D0 D1 D2 D3 D4 0111---0 1000---0 0000---0 0111---0 1000---0 COM0 COM1 COM2 COM3 COM4 -----------
Display data RAM
Organic EL Display
Figure 3 * Write address circuit The write address of the display data RAM is specified using the write address set command as shown in Figures 4-1 to 4-10. Write display data in units of 8 bits in the direction of the common lines, starting at the specified write address. * Column address circuit The column address of the display data RAM is specified using the column address set command as shown in Figures 4-1 to 4-10. Since the specified column address is incremented (by +1) every time a display data read/write command is issued, the MPU can access the display data continuously. Further, the incrementing of the column address is stopped at the column address of 7FH. Since the column address and the write address are independent of each other, it is necessary, for example, to specify separately the new write address and the new column address when changing from column 7FH of write address 07H to column 00H of write address 08H. Also, as is shown in Table 4, it is possible to reverse the correspondence relationship between the display data RAM column address and the SEG output using the ADC command (the anode driver direction select command). This reduces the IC placement restrictions at the time of assembling organic EL modules. Table 4
SEG Output ADC D0 = "0" D0 = "1" SEG0 SEG127 0(H) Column Address 7F(H) 7F(H) Column Address 0(H)
9/53
PEDL9352-01
OKI Semiconductor
ML9352
* Line address circuit The line address circuit is used for specifying the line address corresponding to the COM output when displaying the contents of the display data RAM as is shown in Figures 4-1 to 4-10. The address line is specified depending on whether or not a fixed display line is set. The display area when a fixed display line is not set is equivalent to the number of display lines that are specified to the increment direction of the line address from the specified scroll start address. When the line address exceeds 1FH, it returns to 00H. It is possible to carry out screen scrolling and page changing by changing the line address using the scroll start line address set command. The display area when a fixed display line is specified is equivalent to the number of lines which are calculated by subtracting the number of fixed display lines from the number of display lines that are specified to the increment direction of the line address from the scroll start line address. When the line address exceeds 1FH, it returns to the address next to the fixed display line specified. It is possible to carry out screen scrolling except the fixed display line by changing the line address using the scroll start line address set command. * Display data latch circuit The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being output to the organic EL drive circuits. Since the commands for selecting normal/reverse display and turning the display ON/OFF control the data in this latch, the data in the display data RAM will not be changed.
Oscillator circuit This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when CLS = "L". The oscillations will be stopped when CLS = "H", and the display clock has to be input to the CL pin. The oscillations will also be stopped during the power save mode.
10/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 10 SEG Output ADC
Column Address
Start (Line 1)
Line 32
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 32 lines * Number of fixed display lines: None * Scroll start line address: 00H
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
Figure 4-1
11/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 10 SEG Output ADC
Column Address
Line 32 Start
(Line 1)
Line 15
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 32 lines * Number of fixed display lines: None * Scroll start line address: 11H
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
Figure 4-2
12/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 10 SEG Output ADC
Column Address
Start (Line 1)
Line 8 Line 24
Line 32 Line 9
Line 23
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 32 lines * Number of fixed display lines: 00H to 07H * Scroll start line address: 11H
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
Figure 4-3
13/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Column Address
Start (Line 1)
Line 9 Line 8
Line 32
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 32 lines * Number of fixed display lines: 00H to 07H * Scroll start line address: 06H
Figure 4-4
10 SEG Output ADC
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
14/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Column Address
Start (Line 1)
Line 10
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 10 lines * Number of fixed display lines: None * Scroll start line address: 11H
Figure 4-5
10 SEG Output ADC
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
15/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Column Address
Line 20
Start (Line 1)
Line 15
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 20 lines * Number of fixed display lines: None * Scroll start line address: 11H
Figure 4-6
10 SEG Output ADC
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
16/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Column Address
Start (Line 1)
Line 8
Line 9
Line 18
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 18 lines * Number of fixed display lines: 00H to 07H * Scroll start line address: 11H
Figure 4-7
10 SEG Output ADC
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
17/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Column Address
Start (Line 1)
Line 8 Line 13
Line 18
Line 9 Line 12
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 18 lines * Number of fixed display lines: 00H to 07H * Scroll start line address: 1CH
Figure 4-8
10 SEG Output ADC
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
18/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Column Address
Start (Line 1)
Line 9 Line 8
Line 18
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 18 lines * Number of fixed display lines: 00H to 07H * Scroll start line address: 06H
Figure 4-9
10 SEG Output ADC
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
19/53
PEDL9352-01
OKI Semiconductor
ML9352
Write Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH SEG123 04 7B SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F 00 01 02 03 04 05 06 07
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 10 SEG Output ADC
Column Address
Start (Line 1)
Line 10
COM Output COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0
Normal Reverse
Common output state
* Number of display lines: 10 lines * Number of fixed display lines: 00H to 0FH * Scroll start line address: 10H
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
7F 7E 7D 7C 7B 7A 79 78
Figure 4-10
20/53
PEDL9352-01
OKI Semiconductor
ML9352
Display timing generator circuit This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the anode driver output pin in synchronization with the display clock. The read out of the display data to the organic EL drive circuits is completely independent of the display data RAM access from the MPU. As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed asynchronously during the organic EL display. Also, the internal cathode timing is generated by this circuit from the display clock.
Common output state selection circuit (see Table 5) Since the COM output scanning directions can be set using the common output scan direction select command in the ML9352, it is possible to reduce the IC placement restrictions at the time of assembling organic EL modules. Table 5
State Normal Display Reverse Display COM Scanning direction COM0 COM31 COM31 COM0
* When the number of display lines is 32.
Organic EL Drive circuits The anode driver circuit employs the constant current system and the cathode driver circuit employs the push-pull system. The anode output current is set by the voltage applied to VEL pin, or output voltage of the built-in voltage regulator, and the external resistors connected to the REL1 and REL2 pins. IELA = VEL/REL (Here, IELA: Anode output current; VEL: Voltage applied to VEL pin or the output voltage of built-in voltage regulator; and REL: External resistors connected to the REL1 and REL2 pins.) Selection between the voltage applied to the VEL pin and the output voltage of built-in voltage regulator is by the ELSEL pin. Similarly, selection of REL1 pin or REL2 pin is by the external resistor switching command for adjusting anode output current. When in the power save mode, all operations of the built-in voltage regulator and the organic EL drive circuits are stopped. And the anode and cathode drivers' outputs go to the VSS level.
21/53
PEDL9352-01
OKI Semiconductor
ML9352
* Organic EL Driver Waveform [Command Setting Conditions] Anode driver system set: Set the non-display anode output status to low. Cathode driver system set 1: Set the cathode output status during discharge period to low. Cathode driver system set 2: Set the output status, other than during discharge period of non-selected cathode output, to high. Anode pulse width adjustment: Set to 235/256 Reverse voltage pulse width adjustment: Set to 14/256 Applied reverse voltage setting: Set the reverse voltage to be applied. Static on/off: Set to static ON
1 line display period Discharging duration
1
Display time control period
15 17 253 256
Display clock Anode (Display on) Anode (Display off) Cathode (Selection) Cathode (Selection) Display data: all "0" Cathode (Non-selection) Cathode (Non-selection) Display data: all "0" Applied reverse voltage Display on duration Reset duration Display off
* Cathode Waveform
1 frame 1 line COM1 COM2 COM3 COM4
COMm COMS1
22/53
PEDL9352-01
OKI Semiconductor
ML9352
* Reset circuit This LSI goes into the initialized condition when the RES input goes to the "L" level. The initialized condition consists of the following conditions. (1) Display OFF (2) Normal display mode (3) ADC Select: Forward (ADC command D0 = "L") (4) The registers and data in the serial interface are cleared. (5) Read-modify-write: OFF (6) Scroll start line is set to line 1. (7) The column address is address 0. (8) The write address is 00H. (9) Common output state: Normal (10) A fixed display line is not set. (11) The number of display lines is 32. (12) The anode pulse width adjustment is 0/256. (13) The reverse voltage pulse width adjustment is 16/256. (14) Applied reverse voltage setting OFF (15) The cathode drive system is set to "Low during discharge" and "High during other than discharge in non-selection mode". (16) The anode drive system is set to "Low during display OFF". (17) The anode output current adjusting external resistor is REL1. (18) Static OFF. On the other hand, when the reset command is used, only the conditions (5) to (18) above are set. As is shown in the "MPU Interface (example for reference)", the RES pin is connected to the Reset pin of the MPU and the initialization of this LSI is made simultaneously with the resetting of the MPU. This LSI always has to be reset using the RES pin at the time the power is switched ON. Also, excessive current can flow through this LSI when the control signal from the MPU is in the Hi-Z state. It is necessary to take measures to ensure that the control signal from the MPU does not go into the Hi-Z state after the power has been switched ON. During the period when RES = "L", although the oscillator circuit is operating, the display timing generator would have stopped and the CL pin would have been tied to the "H" level. There is no effect on the pins D0 to D7.
23/53
PEDL9352-01
OKI Semiconductor
ML9352
COMMANDS
MPU Interface
MPU 80-Series 68-Series Read mode Pin RD = "L" Pin R/W = "H" Pin E = "H" Write mode Pin WR = "L" Pin R/W = "L" Pin E = "H"
In the case of the 80-series MPU interface, a command is started by inputting a Low pulse on the RD pin or the WR pin. In the case of the 68-series MPU interface, a command is started by inputting a High pulse on the E pin.
Description of commands * Display ON/OFF (Write) This is the command for controlling the turning on or off the organic EL panel. The organic EL display is turned on when a "1" is written in bit D0 and is turned off when a "0" is written in this bit. While the organic EL panel is turned off, the anode and cathode drivers output the VSS level.
A0 Display ON Display OFF 0 0 D7 1 1 D6 0 0 D5 1 1 D4 0 0 D3 1 1 D2 1 1 D1 1 1 D0 1 0
* Display line number (2-byte command) This command specifies the number of lines to be displayed on the organic EL panel. This command is used together with a pair of the display line number set mode command and the display line number register set command. Be sure to use these two paired commands sequentially. * Display line number set mode (Write) The display line number register set command is enabled by inputting this command. When the display line number set mode is set, commands other than the display line number register set command cannot be used. This status is released when display line number data is set to the register with the display line number register set command.
No. of display lines 32 lines Determined by display line register data A0 0 0 D7 1 1 D6 1 1 D5 0 0 D4 1 1 D3 0 1 D2 * * D1 * * D0 * *
Note: When the number of display lines is set to 32 (D3 = 0), the display line number register set command is disabled.
24/53
PEDL9352-01
OKI Semiconductor
ML9352
* Display line number register set (Write) The number of lines to be displayed on the organic EL panel can be selected by setting 6-bit data to the display line number register with this command. The cathode output pins are fixed to a "H" level except for the outputs that correspond to the selected lines. The display line number set mode is released when the display line number register is set by inputting this command.
No. of display lines 1 2
* * *
A0 0 0
* * *
D7 * *
* * *
D6 * *
* * *
D5 0 0
* * *
D4 0 0
* * *
D3 0 0
* * *
D2 0 0
* * *
D1 0 0
* * *
D0 0 1
* * *
31 32
0 0
* *
* *
1 1
1 1
1 1
1 1
1 1
0 1
* Fixed display line number (2-byte command) This command is used to specify the number of lines, which are not scrolled on the organic EL panel, on an 8-bit unit basis. This command is used together with a pair of the fixed display line number set mode command and the fixed display line number register set command. Be sure to use these two paired commands sequentially. * Fixed display line number set mode (Write) The fixed display line number register set command is enabled by inputting this command. When the fixed display line number set mode is set, commands other than the fixed display line number register set command cannot be used. This status is released when fixed display line number data is set to the register with the fixed display line number register set command.
No. of fixed display lines None Determined by fixed display line register data A0 0 0 D7 1 1 D6 0 0 D5 0 0 D4 1 1 D3 0 1 D2 * * D1 * * D0 * *
Note:
When the fixed display line is not set (D3 = 0), the fixed display line number register set command is disabled.
* Fixed display line number register set (Write) The number of lines not to be scrolled on the organic EL panel can be selected on an 8-bit unit basis by setting 3-bit data to the fixed display line number register with this command. The fixed display line number set mode is released when the fixed display line number register is set by inputting this command.
Fixed display line address 00H to 07H 00H to 0FH 00H to 17H 00H to 1FH A0 0 0 0 0 D7 * * * * D6 * * * * D5 * * * * D4 * * * * D3 * * * * D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 1
25/53
PEDL9352-01
OKI Semiconductor
ML9352
* Scroll start line set (Write) This command specifies the scroll start line address in the display data RAM. The scroll start line is specified by using the scroll start line set command. It is possible to scroll the display screen by dynamically changing the address using the scroll start line set command.
Line address 00H 01H 02H
* * *
A0 0 0 0
* * *
D7 0 0 0
* * *
D6 1 1 1
* * *
D5 0 0 0
* * *
D4 0 0 0
* * *
D3 0 0 0
* * *
D2 0 0 0
* * *
D1 0 0 1
* * *
D0 0 1 0
* * *
1EH 1FH
0 0
0 0
1 1
0 0
1 1
1 1
1 1
1 1
0 1
* Write Address Set (2-byte command) This command specifies the write data of the display data RAM. Since this is a 2-byte command used with a pair of the write address set mode command and the write address register set command, be sure to use these two commands sequentially. The display data RAM allows access to a desired bit by specifying the write address and the column address. * Write Address Set Mode (Write) The write address register set command is enabled by inputting this command. When once set to the write address set command, commands other than the write address register set command cannot be used. This status is released when the write address data is set by the write address register set command.
A0 0 D7 1 D6 0 D5 1 D4 1 D3 * D2 * D1 * DO *
* Write address register set (Write) This command specifies the write address of the display data RAM by setting 6-bit data to the write address register. The write address set mode is released when the write address register is set by inputting this command.
Write address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H
* * *
A0 0 0 0 0 0 0 0 0 0 0
* * *
D7 * * * * * * * * * *
* * *
D6 * * * * * * * * * *
* * *
D5 0 0 0 0 0 0 0 0 0 0
* * *
D4 0 0 0 0 0 0 0 0 0 0
* * *
D3 0 0 0 0 0 0 0 0 1 1
* * *
D2 0 0 0 0 1 1 1 1 0 0
* * *
D1 0 0 1 1 0 0 1 1 0 0
* * *
D0 0 1 0 1 0 1 0 1 0 1
* * *
1EH 1FH
0 0
* *
* *
0 0
1 1
1 1
1 1
1 1
0 1
26/53
PEDL9352-01
OKI Semiconductor
ML9352
* Column address set (Write) This command specifies the column address of the display data RAM. The column address is specified by successively writing the upper 4 bits and the lower 4 bits. Since the column address is automatically incremented (by +1) every time the display data RAM is accessed, the MPU can read or write the display data continuously. The incrementing of the column address is stopped at the address 7FH.
A0 Upper bits Lower bits Column address 00H 01H 02H
* * *
D7 0 0 a6 0 0 0
* * *
D6 0 0 a5 0 0 0
* * *
D5 0 0 a4 0 0 0
* * *
D4 1 0 a3 0 0 0
* * *
D3 a7 a3 a2 0 0 0
* * *
D2 a6 a2 a1 0 0 1
* * *
D1 a5 a1 a0 0 1 0
* * *
D0 a4 a0
0 0 a7 0 0 0
* * *
7EH 7FH
0 0
1 1
1 1
1 1
1 1
1 1
1 1
0 1
* Status read (Read)
A0 0 BUSY D7 BUSY D6 ADC D5 ON/OFF D4 RESET D3 0 D2 0 D1 0 D0 0
When BUSY is `1', it indicates that the internal operations are being made or the LSI is being reset. Although no command is accepted until BUSY becomes `0', there is no need to check this bit if the cycle time can be satisfied. This bit indicates the relationship between the column address and the segment driver. 0: Reverse (SEG127 SEG0; column address 0H 7FH) 1: Forward (SEG0 SEG127; column address 0H 7FH) (Opposite to the polarity of the ADC command.)
ADC
ON/OFF
This bit indicates the ON/OFF state of the display. (Opposite to the polarity of the display ON/OFF command.) 0: Display ON 1: Display OFF
RESET
This bit indicates that the LSI is being reset due to the RES signal or the reset command. 0: Operating state 1: Being reset
* Display data write (Write) This command writes an 8-bit data at the specified address of the display data RAM. Since the column address is automatically incremented (by +1) after writing the data, the MPU can write the display data to the display data RAM continuously.
A0 1 D7 D6 D5 D4 D3 D2 D1 D0
Write data
27/53
PEDL9352-01
OKI Semiconductor
ML9352
* Display data read (Read) This command read the 8-bit data from the specified address of the display data RAM. Since the column address is automatically incremented (by +1) after reading the data, the MPU can read display data from the display data RAM continuously. Further, one dummy read operation is necessary immediately after setting the column data. The display data cannot be read out when the serial interface is being used.
A0 1 D7 D6 D5 D4 D3 D2 D1 D0
Read data
* ADC Select (segment driver direction select) (Write) Using this command it is possible to reverse the relationship of correspondence between the column address of the display data RAM and the segment driver output. It is possible to reverse the sequence of the segment driver output pin by the command.
A0 Forward Reverse 0 0 D7 1 1 D6 0 0 D5 1 1 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 1
* Normal/reverse display mode (Write) It is possible to toggle the display on and off condition without changing the contents of the display data RAM. In this case, the contents of the display data RAM will be retained.
A0 Forward Reverse 0 0 D7 1 1 D6 0 0 D5 1 1 D4 0 0 D3 0 0 D2 1 1 D1 1 1 D0 0 1 RAM Data Organic EL ON when "H" Organic EL ON when "L"
* Display all-ON/OFF (Write) Using this command, it is possible to forcibly turn ON all the dots in the display irrespective of the contents of the display data RAM. In this case, the contents of the display data RAM will be retained. This command is given priority over the Normal/reverse display mode command.
A0 Normal display state All-on display 0 0 D7 1 1 D6 0 0 D5 1 1 D4 0 0 D3 0 0 D2 1 1 D1 0 0 D0 0 1
The power save mode will be entered into when the Display all-ON command is executed in the display OFF condition. * Read-modify-write (Write) This command is used in combination with the End command. When this command is issued once, the column address is not changed when the Display data read command is issued, but is incremented (by +1) only when the Display data write command is issued. This condition is maintained until the End command is issued. When the End command is issued, the column address is restored to the address that was effective at the time the Read-modify-write command was issued last. Using this function, it is possible to reduce the overhead on the MPU when repeatedly changing the data in special display area such as a blinking cursor.
A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
28/53
PEDL9352-01
OKI Semiconductor
ML9352
* End (Write) This command releases the read-modify-write mode and restores the column address to the value at the beginning of the read-modify-write mode.
A0 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
Restored Column address N N+1 N+2 N+3 .... N+m N End
Read-modify-write mode set
* Reset (Write) This command initializes the scroll start line number, column address, page address, common output state, fixed display line, number of display lines, anode pulse width adjustment, cathode driving, and anode driving, and also releases the read-modify-write mode and the test mode. This command does not affect the contents of the display data RAM. The reset operation is made after issuing the reset command. The initialization after switching on the power is carried out by the reset signal input to the RES pin.
A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
* Common output scan direction select (Write) This command is used for selecting the scanning direction of the COM output pins.
ML9352 Forward Reverse COM0 COM31 COM31 COM0 A0 0 0 D7 1 1 D6 1 1 D5 0 0 D4 0 0 D3 0 1 D2 * * D1 * * D0 * *
*: Invalid bits * Cathode drive set 1 (Write) This command is used to select an output state of the cathode drive circuit during discharging.
Cathode output state Low High A0 0 0 D7 1 1 D6 0 0 D5 1 1 D4 0 0 D3 0 0 D2 0 0 D1 1 1 D0 0 1
* Cathode drive set 2 (Write) This command is used to select an output state of the unselected cathode drive circuit during other than discharging.
Cathode output state High High impedance A0 0 0 D7 1 1 D6 0 0 D5 1 1 D4 0 0 D3 1 1 D2 0 0 D1 1 1 D0 0 1
29/53
PEDL9352-01
OKI Semiconductor
ML9352
* Anode drive set (Write) This command is used to select an output state of the anode drive circuit during display-OFF condition.
Anode output state Low High impedance A0 0 0 D7 1 1 D6 0 0 D5 1 1 D4 0 0 D3 1 1 D2 0 0 D1 0 0 D0 0 1
* Anode pulse width adjustment (Write) This command specifies the output pulse width of the anode driver outputs (SEG0 to SEG127). This allows a luminance of the organic EL panel to be set. This command is used together with a pair of the anode pulse width adjustment set mode command and the anode pulse width adjustment register set command. Be sure to use these paired commands sequentially. * Anode pulse width adjustment set mode (Write) The anode pulse width adjustment register set command is enabled by setting this command. When the anode pulse width adjustment set mode is set, commands other than the anode pulse width adjustment register set command cannot be used. This state is released by setting anode pulse width adjustment data to the register.
A0 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
* Anode pulse width adjustment register set (Write) The duty of anode driver output pulse width is set between 0/256 and 240/256 by setting 8-bit data to the anode pulse width adjustment register using this command. If 8-bit data (D7 to D0) is set with F0h to FFh, the output pulse width (duty) becomes 240/256. When the anode pulse width adjustment register is set by inputting this command, the anode pulse width adjustment set mode is released.
Output pulse width (Duty) 0/256 1/256 2/256 * 239/256 240/256 * 240/256 A0 0 0 0 * 0 0 * 0 D7 0 0 0 * 1 1 * 1 D6 0 0 0 * 1 1 * 1 D5 0 0 0 * 1 1 * 1 D4 0 0 0 * 0 1 * 1 D3 0 0 0 * 1 0 * 1 D2 0 0 0 * 1 0 * 1 D1 0 0 1 * 1 0 * 1 D0 0 1 0 * 1 0 * 1
* Reverse voltage pulse width adjustment (Write) This command specifies the pulse width for the reverse voltage applying duration (applying reverse voltage makes all anode outputs low and all cathode outputs high). This command is used together with a pair of the reverse voltage pulse width adjustment set mode command and the reverse voltage pulse width adjustment register set command. Be sure to use these paired commands sequentially.
30/53
PEDL9352-01
OKI Semiconductor
ML9352
* Reverse voltage pulse width adjustment set mode (Write) The reverse voltage pulse width adjustment register set command is enabled by setting this command. When the reverse voltage pulse width adjustment set mode is set, commands other than the reverse voltage pulse width adjustment register set command cannot be used. This state is released by setting reverse voltage pulse width adjustment data to the register.
A0 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
* Reverse voltage pulse width adjustment register set (Write) The pulse width for the reverse voltage applying duration (applying reverse voltage makes all anode outputs low and all cathode outputs high) is set between 0/256 and 16/256 by setting 4-bit data to the reverse voltage pulse width adjustment register using this command. When the reverse voltage pulse width adjustment register is set by inputting this command, the reverse voltage pulse width adjustment set mode is released.
Reverse voltage pulse width 16/256 14/256 12/256 10/256 8/256 6/256 4/256 2/256 0/256 A0 0 0 0 0 0 0 0 0 0 D7 * * * * * * * * * D6 * * * * * * * * * D5 * * * * * * * * * D4 * * * * * * * * * D3 0 0 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 0 D1 0 0 1 1 0 0 1 1 0 D0 0 1 0 1 0 1 0 1 0
* Applied reverse voltage setting (Write) Selects whether to apply the reverse voltage during the discharge interval. Valid only when, in the cathode drive set 1, the cathode output status during the discharge interval has been set to low.
Cathode output state Applied reverse voltage setting off Applied reverse voltage setting on A0 0 0 D7 1 1 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 1 D1 0 0 D0 0 1
* Switching of anode output current adjusting external resistor (Write) This command selects connection pin REL1 or REL2 of the external resistor for adjusting anode output current.
Select pin REL1 REL2 A0 0 0 D7 1 1 D6 0 0 D5 0 0 D4 0 0 D3 1 1 D2 0 0 D1 1 1 D0 0 1
31/53
PEDL9352-01
OKI Semiconductor
ML9352
* Static ON/OFF (Write) This is an operation control command of the cathode driver output (COMS1) for static display. When a "1" is written in bit D0, COMS1 operates and it is possible to carry out the static display. On the other hand, when a "0" is written in bit D0, COMS1 goes high and the static display is turned off.
Select pin Static ON Static OFF A0 0 0 D7 1 1 D6 0 0 D5 1 1 D4 0 0 D3 1 1 D2 1 1 D1 0 0 D0 1 0
* Power save (Compound command) The power save mode is entered when the display all-ON command is executed in the display OFF condition. This mode can greatly reduce the current consumption. When in the power save mode, the display data and operating mode remain unchanged, and also it is possible to access the display data RAM from the MPU. The power save mode is released by using the display all-OFF command. * Power save mode When in the power save mode, all operations of the organic EL driving circuit are stopped. When there is no access from the MPU, the current consumption can be reduced to nearly the static current. The internal circuit conditions in the power save mode are described below. (1) The oscillation circuit stops. (2) The voltage regulator stops. (3) All the organic EL driving circuits stop and the anode and cathode drivers output the VSS level. * NOP (Write) This is a No Operation command.
A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1
* Test (Write) This is a command for testing the IC chip. Do not use this command. When the test command is issued by mistake, this state can be released by issuing a NOP command. This command will be ineffective if the TEST0 pin is open or at the "L" level.
A0 0 D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 *
*: Invalid bits
32/53
PEDL9352-01
OKI Semiconductor
ML9352
LIST OF COMMANDS
No 1 Operation (ML9352) Display OFF Display ON Display line number set 2 Dn 43 01 01 10 11 A0 RD WR 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 Comment
7 1 1 1 1
6 0 0 1 1 * 0 0 * 1 0 * 0 0
5 1 1 0 0
210 110 111 *** ***
Display line number register * set 1 Fixed display line number set 1 3 Fixed display line number register set 4 Scroll start line set 5 Write address set mode Write address register set * 0 1 *
No. of display lines 01 01 * * 0 1 * * * * * * *
0 EL display OFF 0 EL display ON 0 32-line display 0 Sets the number of display lines to the 0 display line number register. 0 Without a fixed display line 0 Sets the number of fixed display lines to the fixed display line number 0 register. 0 Sets the scroll start line address of the display data RAM.
No. of fixed display 0 lines
Display start line address 11**** Write address 01 00
0 0 0
0 Sets the write address of the display 0 data RAM. 0 0 1 Sets the upper 4 bits of column address of the display data RAM. Sets the lower 4 bits of column address of the display data RAM.
Column address set (upper) 0 6 Column address set (lower) 0 7 Status read 8 Display data write 9 Display data read ADC select forward 10 ADC select reverse Normal display Reverse display Normal display 12 Display all-ON 11 13 Read-modify-write 14 End 15 Reset Scanning COM outputs in forward direction Scanning COM outputs in reverse direction 1 1 1 1 1 1 1 1 1 1 1 17 Cathode drive set 1 1 1
Column address 0 (Upper) Column address 0 (Lower)
Status
0
000
0 1 1 0
Write data Read data 0 10 0 000
Reads the status information using the upper 4 bits. 0 Writes data to the display data RAM. 1 Reads data from the display data RAM.
0 0 0 0 0 1 1 1 1 1 0 0
10 1 1 1 1 0 0 0 0
0 0 0 0 0 0 1 0 0 1 0 0
001 1 1 1 1 1 1 0 0 0 1 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
Correspondence between the display 0 data RAM address and SEG output (Forward) Correspondence between the display 0 data RAM address and SEG output (Reverse) 0 EL display normal 0 EL display reverse 0 Normal EL display 0 EL display all ON 0 Increments the column address (by +1) during a write only. 0 Releases the read-modify-write state. 0 Internal reset 0 0 0 0 COM output scanning direction forward COM output scanning direction reverse Cathode driver output "L" level during discharging Cathode driver output "H" level during discharging
10 10 10 00 00 10 10
000 110 010 * * * * * *
16
010 011
33/53
PEDL9352-01
OKI Semiconductor
ML9352
No
Operation (ML9352) 7 1 6 0
Dn 543 101 2 0 1 1 0 0
A0 RD WR 0 1 0
Comment Unselected Cathode driver output "H" level during other than discharging
18 Cathode drive set 2 1 0 101 0 1 1 0 1
Unselected Cathode driver is high 0 impedance during other than discharging 0 0 Anode driver output "L" level during display OFF Anode driver output high impedance during display OFF
1 19 Anode drive set 1 Anode pulse width adjustment set Anode pulse width adjustment register set Reverse voltage pulse width adjustment set mode Reverse voltage pulse width adjustment register set Applied reverse voltage setting 1 * 1 1 1 1 1 1 1
0 0 0
101 101 000
0 0 0
0 0 0
0 1 1
0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
20
Pulse width data 0 * 0 0 0 0 0 0 000 * * 0 1 0
0 Sets the anode pulse width data to the anode pulse width adjustment 0 register. Sets the data of the pulse width of the reverse voltage applying duration to the reverse voltage pulse width 0 adjustment register. 0 0 Applied reverse voltage setting OFF 0 Applied reverse voltage setting ON 0 Selects the REL1 pin. 0 Selects the REL2 pin. 0 Cathode driver for static display (COMS1) operates. Compound command of display OFF and display all ON
0 0 0 0 0 0 0 0
21
Pulse width data 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0
22
000 000 001 001 101 101
Switching of the anode 23 output current adjusting external resistor 24 Static ON Static OFF 25 Power save 26 NOP 27 Test
0 COMS1 always "H".
1 1
1 1
100 11 *
0 *
1 *
1 *
0 0
1 1
0 The "No Operation" command 0 The command for factory testing of the IC chip
*: Invalid data
34/53
PEDL9352-01
OKI Semiconductor
ML9352
DESCRIPTION OF COMMANDS
Examples of settings for the instructions (reference examples) * Initial setting
VDD-VSS power supply ON *1 VDISP-VSS power supply ON Whichever of the two power supplies, VDISP or VDD, is turned on first, it does not matter. Power supply stabilization Change the RES pin level from "L" to "H" Wait for at least 20 ms *2 Initial settings state (default) Function stabilization using command input (user settings) *3
Initial setting state complete Wait for at least 20 ms Display ON
Notes: Sections to be referred to *1: VDD: VDDA and VDDL VDISP: VDISPS and VDISPC VSS: VSSA, VSSL, VSSS, and VSSC *2: Stabilization time of the internal oscillator *3: Function description "Reset circuit"
35/53
PEDL9352-01
OKI Semiconductor
ML9352
* Data display
End of initial settings Function stabilization using command input (user settings) Display start line set Write address set Column address set *10 *11 *12
Function stabilization using command input (user settings) Display data write *13
Function stabilization using command input (user settings) Display ON/OFF End of data display *14
Notes: *10: *11: *12: *13: *14:
Sections to be referred to Command description "Display start line set" Command description "Write address set" Command description "Column address set" Command description "Display data write" Command description "Display ON/OFF"
* Power supply OFF
Any state Function stabilization using command input (user settings) Power save VDISP-VSS, VDD-VSS power supply OFF *15 *16
Notes: Sections to be referred to *15: Command description "Power save" *16: Do not enter Reset when switching the power supply OFF. VDD: VDDA and VDDL VDISP: VDISPS and VDISPC VSS: VSSA, VSSL, VSSS, and VSSC
36/53
PEDL9352-01
OKI Semiconductor
ML9352
* Refresh To avoid malfunction or erroneous display, it is recommended to use the refresh sequence at regular intervals.
Refresh sequence Set to the state in which all commands have been set. Test mode release command (E3h) Refresh display data RAM
37/53
PEDL9352-01
OKI Semiconductor
ML9352
ABSOLUTE MAXIMUM RATINGS
VSS = 0 V Parameter Power supply voltage EL drive voltage EL reference voltage Logic input voltage Anode output voltage Cathode output voltage Anode output current Cathode output current Storage temperature range Symbol VDD VDISP VEL VI VELA VELK IELA IELK Tstg Condition Ta = 25C Ta = 25C -- Ta = 25C Ta = 25C Ta = 25C during "L" level output during "H" level output during "L" level output during "H" level output Chip Rating -0.3 to +6.5 -0.3 to +35 -0.3 to VDISPS -0.3 to VDD+0.3 -0.3 to VDISPS+0.3 -0.3 to VDISPC+0.3 0.0 to 30 -1.0 to 0.0 0.0 to 150 -70 to 0.0 -55 to +125 Unit V V V V V V mA mA C Applicable pins VDD, VSS VDISP, VSS VEL, VSS All logic inputs SEG0 to 127 COM0 to 31, COMS1 SEG0 to 127 COM0 to 31, COMS1 --
Ta: VDD: VDISP: VSS:
Ambient temperature VDDA and VDDL VDISPS and VDISPC VSSA, VSSL, VSSS, and VSSC
RECOMMENDED OPERATING CONDITIONS
VSS = 0 V Parameter Power supply voltage EL drive voltage EL reference voltage Anode output voltage Cathode output voltage "H" anode output current "L" anode output current (during charging or discharging of the panel capacitance) "H" cathode output current (during charging or discharging of the panel capacitance) "L" cathode output current Operating temperature range Symbol VDD VDISP VEL VELA VELC IELA IELA Condition -- -- -- -- -- -- -- Range 2.7 to 5.5 18 to 30 4 to VDISPS/3 -0.3 to VDISPS-5 -0.3 to VDISPC -0.8 to -0.1 0 to 20 Unit V V V V V mA mA SEG0 to 127 Applicable pins VDD, VSS VDISP, VSS VEL, VSS SEG0 to 127 COM0 to 31, COMS1
IELK IELK Tjop
-- -- --
-50 to 0 0 to 100 -40 to +125
mA mA C
COM0 to 31, COMS1 --
VDD: VDDA and VDDL VDISP: VDISPS and VDISPC VSS: VSSA, VSSL, VSSS, and VSSC
38/53
PEDL9352-01
OKI Semiconductor
ML9352
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 5.5 V, VDISP = 18 to 30 V, VSS = 0 V, Tjop = -40 to +125C) Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current "L" input current "H" input current Anode driver average output current 1 *6 Anode driver output current dispersion within IELA11 the LSI chip 1 *7 Anode driver output current dispersion within IELA21 8 contiguous bits 1 *8 Anode driver average output current 2 *6 Anode driver output current dispersion within IELA12 the LSI chip 2 *7 Anode driver output current dispersion within IELA22 8 contiguous bits 2 *8 Anode driver average output current 3 *6 Anode driver output current dispersion within IELA13 the LSI chip 3 *7 Anode driver output current dispersion within IELA23 8 contiguous bits 3 *8 -IELA2 Symbol VIH VIL VOH VOL IIH1 IIL IIH2 Condition -- IOH = -0.5 mA IOL = 0.5 mA VI = VDD VI = 0 V VI = VDD ELSEL = "H" VEL = 5 V REL2 = 7.2 k VOH = VDISPS - 8 V ELSEL= "H" VEL = 5 V REL2 = 7.2 k VOH = VDISPS - 8 V ELSEL = "H" VEL = 5 V REL2 = 7.2 k VOH = VDISPS -8 V ELSEL = "L" REL2 = 7.2 k VOH = VDISPS - 8 V ELSEL = "L" REL2 = 7.2 k VOH = VDISPS - 8 V ELSEL = "L" REL2 = 7.2 k VOH = VDISPS - 8 V ELSEL = "H" VEL = 5 V REL1 = 24.7 k VOH = VDISPS - 8 V ELSEL = "H" VEL = 5 V REL1 = 24.7 k VOH = VDISPS - 8 V ELSEL = "H" VEL = 5 V REL1 = 24.7 k VOH = VDISPS - 8 V Min. 0.8 x VDD VSS 0.8 x VDD VSS -10 5 Typ. -- -- -- -- Max. VDD 0.2 x VDD VDD 0.2 x VDD +10 200 Unit V V A A A Applicable pins *1 *2 *3 *4 *5
-IELA1
-724
-694
-664
SEG0 to 127
-5
0
+5
%
SEG0 to 127
-4
0
+4
%
SEG0 to 127
-770
-694
-617
A
SEG0 to 127
-5
0
+5
%
SEG0 to 127
-4
0
+4
%
SEG0 to 127
-IELA3
-212
-202
-192
A
SEG0 to 127
-5
0
+5
%
SEG0 to 127
-4
0
+4
%
SEG0 to 127
39/53
PEDL9352-01
OKI Semiconductor
ML9352
Parameter Anode driver average output current 4 *6
Symbol
Condition ELSEL = "L" REL1 = 24.7 k VOH = VDISPS - 8 V ELSEL = "L" REL1 = 24.7 k VOH = VDISPS - 8 V ELSEL = "L" REL1 = 24.7 k VOH = VDISPS - 8 V ELSEL = "H" VEL = 5 V REL2 = 7.2 k VOH VDISPS - 3 V ELSEL = "H" VEL = 5 V REL1 = 24.7 k VOH VDISPS - 3 V ELSEL = "H" VEL = 5 V VOH = 10 V REL2 = 7.2 k VDISPS = 18 to 30 V ELSEL = "H" VEL = 5 V VOH = 10 V REL1 = 24.7 k VDISPS = 18 to 30 V VDISPS = 18 V VO = 18 V VDISPC = 18 V VO = 1 V
Only one output is "L".
Min.
Typ.
Max.
Unit A
Applicable pins SEG0 to 127
-IELA4
-224
-202
-180
Anode driver output current dispersion within IELA14 the LSI chip 4 *7 Anode driver output current dispersion within IELA24 8 contiguous bits 4 *8 Output voltage fluctuation to anode driver output IELA31 current 1 *9 Output voltage fluctuation to anode driver output IELA32 current 2 *9 VDISP voltage fluctuation to anode driver output IELA41 current 1 *10 VDISP voltage fluctuation to anode driver output IELA42 current 2 *10 Anode driver "L" output current Cathode driver "L" output current Cathode driver "H" output current Voltage regulator output Input pin capacitance Internal oscillation External input IELAL
-5
0
+5
%
SEG0 to 127
-4
0
+4
%
SEG0 to 127
-2.5
--
--
%/V
SEG0 to 127
-2.0
--
--
%/V
SEG0 to 127
--
--
+2.0
%/V
SEG0 to 127
--
--
+2.0
%/V
SEG0 to 127
20
--
--
mA
SEG0 to 127 COM0 to 31, COMS1 COM0 to 31, COMS1 TEST5
lELCL
100
--
--
mA
lELC1H VREG CIN fOSC fCL fOSCADJ
VDISPC = 18 V VO = 0 V -- Ta = 25C, f = 1 MHz -- -- Connect ROSC to VSSL
-50 4.7 -- 3.07 32 -20
-- 5 5 4.05 -- -16
-- 5.3 8 5.33 1000 -12
mA V pF MHz kHz %
Oscillator frequency
*11 CL*5
Internal oscillator frequency adjustment
40/53
PEDL9352-01
OKI Semiconductor
ML9352
*1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11:
A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, C86, P/S, RES, ELSEL D0 to D7, CL A0, RD (E), WR (R/W), CS1, CS2, RES Applicable to the pins D0 to D5, D6 (SCL), D7 (SI), and CL in the high impedance state. CLS, C86, P/S, ELSEL The average of output currents of SEG0 to SEG127 Each output current from SEG0 to SEG127 divided by the average of output currents of SEG0 to SEG127 Each output current from SEG8n to SEG8n+7 divided by the average of output currents of SEG8n to SEG8n+7: n = 0 to 15 {[I(VO = VDISPS - 8 V) - I(VO = VDISP - n V)]/[(VDISPS - 8 V) - (VDISP - n V)]}/I(VO = VDISPS - 8 V) x 100 {[I(VDISP = n V) - I(VDISPS = 18 V)]/(n V - 18 V)}/I(VDISPS = 18 V) x 100 See Table 24 for the relationship between the oscillator frequency and the frame frequency.
VDD: VDDA and VDDL VDISP: VDISPS and VDISPC VSS: VSSA, VSSL, VSSS, and VSSC
41/53
PEDL9352-01
OKI Semiconductor
ML9352
Table 24 Relationship among the oscillator frequency (fOSC), display clock frequency (fCL), and Organic EL frame frequency (fFR)
When the internal oscillator is used No. of display lines 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Frame frequency (Hz) 124.92 124.92 124.92 124.92 119.92 124.92 142.76 124.92 133.25 119.92 136.27 124.92 115.31 142.76 133.25 124.92 117.57 133.25 126.23 119.92 114.21 136.27 130.35 124.92 119.92 115.31 111.04 142.76 137.84 133.25 128.95 124.92 Error (Hz) 0.0 0.0 0.0 0.0 -5.08 0.0 17.76 0.0 8.25 -5.08 11.27 0.0 -9.69 17.76 8.25 0.0 -7.43 8.25 1.23 -5.08 -10.79 11.27 5.35 0.0 -5.08 -9.69 -13.96 17.76 12.84 8.25 3.95 0.0
Note:
The above values apply when fOSC = 3.07 MHz.
Parameter Display clock frequency (fCL) External input Organic EL frame frequency (fFR) fCL/(256 x No. of display lines)
When the internal oscillator is not used
42/53
PEDL9352-01
OKI Semiconductor
ML9352
* Operating current consumption value (VDD = 2.7 to 5.5 V, VDISP = 18 to 30 V, VSS = 0 V, Tjop = -40 to +125C) (1) During display operation Display mode: All-white (When an organic EL panel is not connected)
Symbol lDDA lDDL lDISPS lDISPC Condition VDD = 3 V, VDISP = 30 V VDD = 5 V, VDISP = 30 V VDD = 3 V, VDISP = 30 V VDD = 5 V, VDISP = 30 V VDISPS = 30 V VDISPC = 30 V Min. -- -- -- -- -- -- Typ. -- -- -- -- -- -- Max. 1.0 1.5 1.5 2.5 3.0 1.0 mA Unit Remarks
Display mode: Checker pattern (When an organic EL panel is not connected)
Symbol lDDA lDDL lDISPS lDISPC Condition VDD = 3 V, VDISP = 30 V VDD = 5 V, VDISP = 30 V VDD = 3 V, VDISP = 30 V VDD = 5 V, VDISP = 30 V VDISPS = 30 V VDISPC = 30 V Min. -- -- -- -- -- -- Typ. -- -- -- -- -- -- Max. 1.0 1.5 1.5 2.5 3.0 1.0 mA Unit Remarks
* Power save current consumption (VDD = 2.7 to 5.5 V, VDISP = 18 to 30 V, VSS = 0 V, Tjop = -40 to +125C)
Symbol lDDAS lDDLS lDISPSS lDISPCS Condition During the power save mode During the power save mode During the power save mode During the power save mode Min. -- -- -- -- Typ. -- -- -- -- Max. 10.0 50.0 20.0 50.0 A Unit Remarks
VDD: VDDA and VDDL VDISP: VDISPS and VDISPC VSS: VSSA, VSSL, VSSS, and VSSC
43/53
PEDL9352-01
OKI Semiconductor
ML9352
Timing Characteristics * System bus read/write characteristics 1 (80-series MPU)
A0 tAW8 CS1 (CS2 = "1") tCYC8 WR, RD tCCLR, tCCLW tCCHR, tCCHW tDS8 D0 to D7 (Write) tACC8 D0 to D7 (Read) tOH8 tDH8 tAH8
(VDDA = VDDL = 4.5 to 5.5 V, VSSA = VSSL = 0 V, Tjop = -40 to +125C) Parameter Address hold time Address setup time System cycle time Control "L" pulse width (WR) Control "L" pulse width (RD) Control "H" pulse width (WR) Control "H" pulse width (RD) Data setup time Data hold time RD access time Output disable time Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF Condition Min. 0 0 166 30 30 30 30 30 10 -- 5 Max. -- -- -- -- -- -- -- -- -- 30 50 ns Unit
44/53
PEDL9352-01
OKI Semiconductor
ML9352
(VDDA = VDDL = 2.7 to 4.5 V, VSSA = VSSL = 0 V, Tjop = -40 to +125C) Parameter Address hold time Address setup time System cycle time Control "L" pulse width (WR) Control "L" pulse width (RD) Control "H" pulse width (WR) Control "H" pulse width (RD) Data setup time Data hold time RD access time Output disable time Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF Condition Min. 0 0 400 60 120 60 60 40 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Unit
Note 1:
Note 2: Note 3:
The input signal rise and fall times are specified as 15 ns or less. When using the system cycle time for fast speed, the specified values are (tr + tf) (tCYC8 - tCCLW - tCCHW) or (tr + tf) (tCYC8 - tCCLR - tCCHR). All timings are specified taking the levels of 20% and 80% of VDD as the reference. The values of tCCLW and tCCLR are specified during the overlapping period of CS1 at "L" (CS2 = "H") and the "L" levels of WR and RD, respectively.
45/53
PEDL9352-01
OKI Semiconductor
ML9352
* System bus read/write characteristics 2 (68-series MPU)
A0 R/W tAW6 CS1 (CS2 = "1") tCYC6 tEWHR, tEWHW E tEWLR, tEWLW tDS6 D0 to D7 (Write) tACC6 D0 to D7 (Read) tOH6 tDH6 tAH6
(VDDA = VDDL = 4.5 to 5.5 V, VSSA = VSSL = 0 V, Tjop = -40 to +125C) Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable "H" pulse width Enable "L" pulse width Read Write Read Write Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW Condition -- -- -- CL = 100 pF -- -- Min. 10 10 166 30 10 -- 5 30 30 40 40 Max. -- -- -- -- -- 30 50 -- -- -- -- ns Unit
46/53
PEDL9352-01
OKI Semiconductor
ML9352
(VDDA = VDDL = 2.7 to 4.5 V, VSSA = VSSL = 0 V, Tjop = -40 to +125C) Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable "H" pulse width Enable "L" pulse width Read Write Read Write Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW Condition -- -- -- CL = 100 pF -- -- Min. 10 10 400 40 15 -- 10 120 60 60 60 Max. -- -- -- -- -- 140 100 -- -- -- -- ns Unit
Note 1:
Note 2: Note 3:
The input signal rise and fall times are specified as 15 ns or less. When using the system cycle time for fast speed, the specified values are (tr + tf) (tCYC6 - tEWLW - tEWHW) or (tr + tf) (tCYC6 - tEWLR - tEWHR). All timings are specified taking the levels of 20% and 80% of VDD as the reference. The values of tEWLW and tEWLR are specified during the overlapping period of CS1 at "L" (CS2 = "H") and the "H" level of E.
47/53
PEDL9352-01
OKI Semiconductor
ML9352
* Serial interface
tCSS tCSH
CS1 (CS2 = "1")
tSAS A0
tSAH
tSCYC SCL tf tSLW tSHW
tSDS SI
tSDH
(VDDA = VDDL = 4.5 to 5.5 V, VSSA = VSSL = 0 V, Tjop = -40 to +125C) Parameter Serial clock period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL Time Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Min. 200 75 75 50 100 50 50 100 100 Max. -- -- -- -- -- -- -- -- -- ns Unit
48/53
PEDL9352-01
OKI Semiconductor
ML9352
(VDDA = VDDL = 2.7 to 4.5 V, VSSA = VSSL = 0 V, Tjop = -40 to +125C) Parameter Serial clock period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL Time Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Min. 250 100 100 150 150 100 100 150 150 Max. -- -- -- -- -- -- -- -- -- ns Unit
Note 1: Note 2:
The input signal rise and fall times are specified as 15 ns or less. All timings are specified taking the levels of 20% and 80% of VDD as the reference.
49/53
PEDL9352-01
OKI Semiconductor
ML9352
* Reset input timing
tRW RES tR
Internal state
Being reset
Reset complete
(VDDA = VDDL = 4.5 to 5.5 V, VSSA = VSSL = 0 V, Tjop = -40 to +125C) Parameter Reset time Reset "L" pulse width Symbol tR tRW Condition Min. -- 0.5 Typ. -- -- Max. 0.5 -- Unit ms
(VDDA = VDDL = 2.7 to 4.5 V, VSSA = VSSL = 0 V, Tjop = -40 to +125C) Parameter Reset time Reset "L" pulse width Symbol tR tRW Condition Min. -- 1 Typ. -- -- Max. 1 -- Unit ms
Note 1:
All timings are specified taking the levels of 20% and 80% of VDD as the reference.
50/53
PEDL9352-01
OKI Semiconductor
ML9352
MPU INTERFACE (Reference)
The ML9352 can be connected directly to the 80-series and 68-series MPUs. Further, by using the serial interface, it is possible to operate the LSI with a minimum number of signal lines.
* 80-Series MPU VDD VCC A0 A1 to A7 IORQ MPU D0 to D7 RD WR RES GND RESET Decoder A0 CS1 D0 to D7 RD WR RES VSS P/S VSS ML9352 CS2 VDD C86
* 68-Series MPU VDD VCC A0 A1 to A15 VMA MPU D0 to D7 E R/W RES GND RESET Decoder A0 CS1 D0 to D7 E R/W RES VSS P/S VSS ML9352 CS2 VDD C86
* Serial interface VDD VCC Port 4 A0 CS1 ML9352 MPU Port 3 Port 1 Port 2 RES GND RESET CS2 SI SCL RES VSS P/S VSS
Can be tied to either level.
VDD
C86
51/53
PEDL9352-01
OKI Semiconductor
ML9352
REVISION HISTORY
Document No. PEDL9352-01 Page Date Dec. 27, 2002 Previous Edition - Current Edition - Description Preliminary edition 1
52/53

▲Up To Search▲

Price & Availability of PEDL9352-01

	To Download PEDL9352-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .